Samsung pronounces bottom energy supply community breakthroughs – what does it imply for future chips?

By means of the wanting glass: Many advances in semiconductor know-how hinge on lowering bundle sizes whereas incorporating added performance and extra environment friendly energy supply strategies. Current strategies of energy supply eat vital area on the wafer, resulting in elevated prices, bigger die sizes, and fewer transistors. Earlier this yr, Samsung Semiconductor introduced its analysis on an alternative choice to standard semiconductor energy supply strategies: bottom energy supply. This might result in vital reductions in die dimension and decreased routing congestion.

Based on a report from TheElec and Samsung’s presentation at this yr’s Very Giant Scale Integration (VLSI) Symposium, the semiconductor producer used new bottom energy supply community (BS-PDN) approaches to efficiently scale back the required wafer space by 14.8% when in comparison with conventional entrance aspect energy supply networks (PDNs).

The profitable implementation additionally yielded 10.6% and 19% space reductions in two ARM circuits whereas lowering wiring size by 9.2%.

In conventional frontside PDNs (FSPDNs), semiconductor elements should be organized on the entrance aspect of the wafer in an effort to present transmission from the ability line to the sign line and to the transistors.

This configuration requires shared area and assets between the supply and sign networks, more and more resistant routing to hold electrons throughout the back-end-of-line stack, and can lead to vitality loss throughout transmission to floor rails within the semiconductor construction.

BS-PDN (Bottom Energy Supply Community) is designed to handle these architectural and energy supply limitations. The method fully decouples the ability supply and sign networks and makes use of the bottom of the wafer to accommodate energy distribution. Utilizing the bottom of the wafer, Samsung and different semiconductor producers can as an alternative direct energy supply by shorter, wider traces that supply much less resistance, improved energy supply efficiency, and decreased routing congestion.

Whereas the transfer from FSPDN to BS-PDN sounds promising, there are a number of challenges that forestall it from turning into an ordinary method for producers pursuing the know-how.

One of many greatest challenges to implementing the brand new energy supply mannequin, additionally introduced by Samsung on the symposium, is the potential discount in tensile power related to BS-PDN. When utilized, BS-PDN can scale back the tensile stress acts and through-silicon by way of electrode (TSV), leading to separation from the metallic layer.

Samsung mentioned that this drawback will be solved by lowering the peak or widening the TSV, nonetheless extra analysis and testing is required earlier than an answer will be formally introduced. Extra advances in sign and energy line connectivity will even be required to efficiently apply BS-PDN.

Along with the above, advances in chemical mechanical sprucing (CMP) know-how would even be required. Present CMP implementations are used to take away 5 to 10 microns of “peaks and valleys” from the bottom of a wafer. Implementing BS-PDN may require a brand new strategy to polish the wafer with out damaging the underlying energy elements.

Samsung doesn’t have a present timeline outlining official implementation of BS-PDN-based architectures, however primarily based on present findings and challenges, it is not but clear if we’ll see BS-PDN implementations from Samsung, or different producers like TSMC and Intel, for a number of extra years.

Picture supply: imec-int.com